RISC Emulator

One of the more interesting classes that I am taking this semester is a microprocessor architecture class. The assignment that I have this week is to program an emulator in verilog that simulates the structure of a pipelined RISC CPU. It is a pretty challenging assignment, however I think it is actually very interesting.

Just looking at the diagram and translating it into code seems really interesting to me. Making sure all of the opcodes are accounted for and making sure all of the different components of the CPU are working seems cool. Obviously this is a trivial example, but maybe when I get more time I will look into making an emulator that takes the CPU of say an Atari 2600 or an NES. In any case it would test all of my skills as a Computer Engineer. Going deep down into the hardware does not only require software skills, but also an active understanding of how all the hardware communicates with each other.

That aside, this semester is completely nuts. I am always busy it seems and never really have time to update anything. I will try to keep this updated as much as I can though.

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